The present invention relates to apparatus and methods for providing an output signal proportional to the root-mean-square (RMS) value of an input signal. More particularly, the present invention relates to apparatus and methods for utilizing clock dithering to sampled data to provide an output signal proportional to the RMS value of an input signal having a bipolar signal range. The output signal may be a direct current (DC) signal proportional to the RMS value of an input signal (commonly called RMS-to-DC conversion), or may be a digital signal that has a value that is proportional to the RMS value of an input signal.
There are various known methods for performing RMS-to-DC conversion. Many of these methods utilize continuous time circuits, such thermal and log/anti-log techniques in performing the conversion. Recently, there has been a trend toward utilizing data sampling in accomplishing the conversion. The data sampling may be used in different ways, such as being used as a front end data converter in which analog signals are sampled and converted to digital signals. Under these circumstances, the RMS-to-DC conversion circuitry is entirely digital (see, e.g., E. J. van der Zwan et al., xe2x80x9cA 13 mW 500 kHz Data Acquisition IC with 4.5 Digit DC and 0.02% Accurate True-RMS Extraction,xe2x80x9d IEEE ISSCC99, session 23, paper WP 23.4 (1999)). Alternately, the sampling circuitry may be incorporated into the conversion circuitry so that the output signal remains analog (see, e.g., W. S. Wey, xe2x80x9cA CMOS Delta-Sigma True RMS Converter,xe2x80x9d IEEE Journal of Solid-State Circuits, vol. 35, no. 2, Feb. 2000, pp. 248-257).
These known data sampler converters typically perform the sampling process at a fixed frequency, which may result in aliasing problems and/or bandwidth limitations. With most input waveforms, there should not be a corruption of the conversion process. However, the conversion process may be corrupted when, for example, there is a frequency component aliased on top of another frequency component. For instance, if a fundamental frequency of Fs/4 waveform also has energy at its third harmonic, the third harmonic will alias from 3*Fs/4 to Fs/4, on top of the fundamental. The result may be constructive or destructive, depending on the exact phase of the sampling.
Attempts have been made to address these problems, often utilizing filter circuits to filter out all frequencies above Fs/2. Such techniques, however, must inherently be frequency selective, with an amplitude response that varies with frequency. This may result in a pass-band having a flatness that directly affects the accuracy of the RMS-to-DC conversion. Moreover, the input signal bandwidth of the RMS-to-DC conversion is necessarily constrained to be less than half of the sampling frequency, which can also cause incorrect results when any significant harmonic energy is filtered out.
Therefore, it would be desirable to provide methods and apparatus for performing RMS-to-DC conversion that utilize data sampling techniques without incurring aliasing problems.
It also would be desirable to provide methods and apparatus for performing RMS-to-DC conversion that utilize data sampling techniques that provide for inherent accuracy versus frequency.
In accordance with these and other objects of the present invention, RMS-to-DC converter circuits in accordance with this invention include circuitry that dithers the clock signal used during sampling. The dithering circuits take advantage of the fact that the data itself is sampled at a high frequency, while only a low frequency characterization of the data is necessary. For example, the power distribution grid in most countries is either 50 Hz or 60 Hz, which requires an averaging filter that substantially filters all variations of 20 msec duration or less. These filters, for accuracy at line frequency, are typically just 1-5 Hz. On the other hand, a typical RMS-to-DC converter is constructed using a substantially higher sample frequency, such as 100 kHz.
The present invention dithers the sampling clock signal in a random or random-like manner, such that the input frequency and the sample frequency are highly unlikely to ever be identical, or in an error-prone ratio (i.e., with respect to harmonics). Moreover, the spectrum of the sampling clock need not have a wide bandwidth, as has been used in other applications, such as measurement and electrical interference problems. Instead, the dithering need only have enough jitter over the course of the RMS averaging time constant so as to sample any high frequency input in many xe2x80x9crandomxe2x80x9d phases.
One of the advantages of the present invention is that the selection of a specific RMS-to-DC converter circuit is independent of the present invention. All that is required is that the conversion circuit must be a sampled-data system. For example, the system could utilize a sampling digital-to-analog converter (DAC) as a front end to produce digital sampled data. Then, the digital data could be fed as a data stream to a digital processing system that performs the conversion. Alternately, the sampling system can be incorporated into the RMS-to-DC converter and the converter itself could perform the conversion using entirely analog processing resulting in an analog output signal.